The present invention relates to a surface treatment technology including coating, modification and etching of a surface of a substrate (such as a semiconductor wafer), in particular, to a surface treatment technology using various kinds of beams, such as particle beams, for facilitating reaction of the surface to a source material used in the surface treatment.
With rapid achievement of finer and even more densely packed semiconductor devices, an interconnect (or circuit wiring) pitch has become markedly narrow, and an interconnect electric density has increased considerably. As a result, conventional semiconductor devices comprising an interlayer insulative film layer of silicon oxide and an aluminum-based conductor are confronted with serious problems, i.e. an RC delay phenomenon in signal transmission (i.e. a delay relating to electrical resistance and static capacitance) and electro-migration damage to conductor material. To solve such a problem, it has recently been considered to be essential for conductor material to be changed from presently used aluminum-based material to copper, which has lower electrical resistivity. Further, a coating technology referred to as “chemical vapor deposition (CVD)” has been considered to be most suitable for fabricating such copper interconnects (for example, see NIKKEI MICRODEVICE, December 1998, p.32).
FIG. 1 is a schematic diagram illustrating an exemplary configuration of a coating apparatus used for copper-coating by CVD technology. In FIG. 1, reference numeral 1 designates a reaction chamber which has a susceptor 2 arranged therein for loading a substrate Wf thereon, and is connected to a vacuum evacuation system such as a vacuum pump or the like so as to be decompressed to a specified value P. Reference numeral 3 designates a source material container for containing a source liquid, from which the source liquid is sent to a vaporizer 5 (at a flow rate f) by supplying a carrier gas from a carrier gas container 4 to the source material container 3, so as to be vaporized therein and supplied into the reaction chamber I as a source gas 6. Further, the susceptor 2 is equipped with a heater 7 therein for heating the semiconductor substrate Wf.
In the coating apparatus with a configuration described above, after an inner pressure of the reaction chamber I having been reduced to a predetermined pressure P, the source gas 6 is introduced thereinto from the vaporizer 5 so as for copper included in the source gas to be dissociated and deposited onto a surface of the substrate Wf. As for the source material, an organic complex containing Cu as a component (e.g. hexafluoroacetylacetunate-Cu(I)-trimethylvinyl-silane, liquid under ordinary temperature) is mainly used to be vaporized in the vaporizer 5, and the substrate Wf is heated up to 140 to 180° C. to cause a reaction so that the copper may be deposited on the surface of the substrate Wf, having recesses such as fine via holes and trenches formed therein, for forming an interconnect in a semiconductor device.
FIGS. 2(a) and 2(b) are schematic cross sectional views of a recess, respectively illustrating typical conditions of deposition of copper: 1) coating; and 2) filling thereof. FIG. 2(a) shows a case of coating, in which a diffusion barrier 13 is formed on a surface of a fine recess 12 formed in an insulating layer 11 of a substrate, and a deposited copper layer 14 is formed on the diffusion barrier 13 as a seed layer. FIG. 2(b) shows a case of filling, in which the coating as shown in FIG. 2(a) further proceeds and, as a result, the recess of the surface is finally filled with copper to form a copper layer 15 over the surface with the recess.
As described above, various problems are likely to occur when fine recesses in a surface of a substrate are actually coated or filled with copper by CVD technology. That is, coating or filling the fine recess, with a width equal to or narrower than 0.13 μm, with metal copper by ordinary CVD causes problems such as 1), as shown in FIG. 3(a), a surface of a formed coating film has considerable roughness (bad morphology), and 2), as shown in FIG. 3(b), a defect such as a void or seam is also likely to be produced in copper filled into the recess due to a premature flow-choking forming in an inlet port or mouth of the recess prior to completely filling an interior thereof.
A reason why this phenomenon occurs is considered to be that a trend for a small number of nucleation sites to grow to an abnormally great size is dominant since an activity on a surface of an under-layer is inherently low, and thereby a density of a nucleation site of metal precipitation is made to be extremely low.
As time passes, an island-like deposited copper layer 14 shown in FIG. 3(a) grows in thickness and volume such that each island coalesces with another one to eventually form a continuous film-like deposition, but since density of a nucleation site is low and a number of generated islands is small, the deposited copper layer formed after a certain period of time has a considerable rough surface, which presents an undesirable morphology.
A major reason why the void defect 16, as shown in FIG. 3(b), occurs in the recess 12 is considered to be that in the course of the filling process, the deposited copper layer 15 grows locally at an inlet port of the recess so as to be protruded from each side thereof to bridge the inlet port, and thereby copper is prevented from flowing into the recess.
Since Cu-CVD is typically performed under a pressure of several Torrs to several tens of Torrs, a fluidity of a gaseous phase is under a condition of viscous flow. Accordingly, a source component reaches a surface of a substrate via diffusion passing through a stagnant layer existing near the substrate. A steep gradient in a source concentration generated in the stagnant layer is thought to have a certain relationship with choking of the inlet port.
A deposition rate of copper by CVD has been generally known to be fairly slow in comparison with that of sputter reflow, electroplating or the like.
Indeed, the former hardly exceeds a deposition rate of 200 nm/min, while the latter two easily accomplish a deposition rate of approximately 500 nm/min.
Further, because bonding strength between a copper deposition layer formed by CVD and a substrate surface (surface of the diffusion barrier 13, for example, surface of TaN film) is small, there is a danger that electro-migration resistance might deteriorate. A poor adhesive bonding property as described above is considered to arise from the fact that a lattice incoherence exists between TaN and Cu, and that a surface of a TaN layer formed on the surface of the substrate by conventional sputtering is then oxidized in a surrounding environment so as to be covered by anoxide film.
In connection with this, in order to solve the problem of the RC delay phenomenon in signal transmission and electromigration damage to conductor material, there has been suggested a change of material of an interlayer insulative film layer from the presently used silicon oxide to an organic material having a low dielectric constant, in addition to the above-discussed proposal to change the conductor material to copper. However, even if a diffusion barrier layer of a metal or a compound is deposited in contact with an interlayer insulative film layer of an organic material, a favorable adhesion (bond) strength cannot be obtained by a conventional practice because there is a large difference in properties between materials of these two layers. Accordingly, the diffusion barrier layer is likely to peel or become loose by receiving a thermal or mechanical load after a deposition process. Thus, the conventional practice has a serious problem to be solved.
Organic materials usable in the near future to form an interlayer insulative film layer include siloxane-based organic materials. A typical example thereof is MSQ (Methyl SilsesQuioxane), which is an organic SOD having a methyl group. Examples of pure materials containing no siloxane are organic polymers (e.g. polyaryl ether and aromatic hydrocarbons). These organic materials have a dielectric constant on the order of 2.5 and are therefore considered to be most probable materials for next-generation interconnect structures (see, for example, the August 1999 issue of Electronic Journal, p. 91).
Such an organic material and a metal or compound material commonly used to form a diffusion barrier layer in contact with the organic material are substantially different from each other in general properties, i.e. physical, chemical, thermal and mechanical properties, to say nothing of molecular structure and interatomic (intermolecular) distance, in addition to the fact that the former is an organic material and the latter is an inorganic material. Therefore, it is difficult to make these two materials adhere (bond) to each other. Even if the two materials can be made to adhere (bond) to each other, adhesion strength (bond strength) is very small. Therefore, there is a strong possibility that the two materials will peel or dissociate from each other upon receiving an in-process load during a semiconductor device manufacturing operation or an in-service load, causing an interruption of a manufacturing process or leading to stopping operation after starting of service.
According to the prior art, attempts have been made to create an excellent bonded layer by physically roughening a surface of an insulating layer, serving as an underlayer for a diffusion barrier layer before it is formed, or activating a surface of the insulating layer by a chemical treatment. However, the diffusion barrier layer is originally a very thin film having a thickness of 10 to 50 nanometers. It is therefore difficult to obtain a suitable roughness for this thin diffusion barrier layer, and it is extremely difficult to form inner surfaces of fine recesses in the underlayer (insulating layer) into an optimum surface configuration. Further, a chemical activation treatment may cause pollution problems due to waste fluid. Therefore, it costs a great deal to treat the waste fluid. Accordingly, the chemical activation treatment is not preferable from a practical point of view.
Meanwhile, it is conceivable to bring an active species (e.g. hydrogen radicals) into contact with a surface of an interlayer insulative film layer to thereby reduce a surface of an underlayer or sever an atomic bond thereof in advance (pre-treatment). It is also conceivable to raise a temperature after deposition of a diffusion barrier layer to thereby induce inter-diffusion or form a compound by a reaction between these two layers (post-treatment). However, because of an extremely large difference in physical properties between materials of the two layers, neither the pre-treatment nor the post-treatment produces significant effects. These treatments may produce a contrary result, i.e. formation of a harmful reaction product.
Further, with regard to use of copper as a conductive material during fabrication of a semiconductor device, there is another problem as discussed below.
To date, it has been considered to be quite difficult to perform anisotropic etching (hereinafter referred to as an etching, where appropriate) of Cu by way of a dry etching method using a gas without any liquid agent applied thereto, and actually there has been found no such successful example put into practical use. Among a small number of research papers, there has been reported a result of a case where a reactive ion etching (RIE) was conducted by using a mixed gas composed of SiCl4, Cl2, N2, and NH3 [Arita et al. P.1156 in the Applied Physics, 61, 11 (1992)]. According to this paper, it is reported that a successful processing shape was obtained with an etching rate of about 100 nm/min as shown in FIG. 4. Herein, NH3 gas was added to a material gas for a purpose of forming a protective film of SiN family over a side wall face in order to maintain a directional property of etching. Nevertheless, there has been a problem in that an etching rate decreases as flow rate of NH3 increases, as shown in FIG. 4.
On the other hand, differently from etching of a substrate of a semiconductor, there has been disclosed a technology to be used for removing a copper film deposited within an apparatus for chemical vapor deposition (CVD) of copper, in which the copper film is brought into contact with gaseous hexafluoro-acetylacetone [C5H2O2F6, hereinafter abbreviated as H(hfac)] and oxygen gas so as to form a volatile copper complex compound [Tomoaki Koide et al. 30P-YA-16 in “The proceedings of the 47th Applied Physics Related Association Lecture Meeting” ('00.3)]. This technology has taught that there occurs no reaction with the copper when the copper film is brought into contact With only the H(hfac) gas, but the H(hfac) gas added with O2 gas causes such reactions as oxidization of metal copper as denoted by the following formula (1), and complexing and desorption of copper oxide as denoted by the following formula (2), resulting in a deposited copper film being vaporized and removed.4Cu+O2→2Cu2O 2Cu+O2→2CuO  (1)Cu2O+2H(hfac)→Cu(hfac)2↑+Cu+H2O CuO+2H(hfac)→Cu(hfac)2↑+H2O  (2)
FIG. 5 is a diagram illustrating an example of actual measurement of a removing rate of Cu reported in the above paper. As can be seen from FIG. 5, a copper substrate heated up to 300° C. is etched and removed at a rate of approximately 400 nm/min. However, if the principle disclosed in this paper is applied to an etching process of semiconductor device fabrication without any modifications, there would occur an isotropic etching as shown in FIG. 6, causing considerable disadvantages in wire-patterning of a fabricated semiconductor device.
Referring to FIG. 6, a Si substrate as designated by 17 has an insulation layer 14a, a Cu wiring layer 14, and a resist layer (mask) 18, each of which layers is sequentially built one on another on top of the Si base layer 17, wherein if H(hfac) gas 19 is blown into an aperture 18a of the resist layer 18 to etch the Cu wiring layer 14, resultant etch pit 12 formed by isotropic etching with the H(hfac) gas 19 expands in a lower location of the resist layer 18 to be greater than a cross sectional area of the aperture 18a, thus making it impossible for the etch pit 12 to be formed limitedly in a vertically downward direction from the aperture 18a of the resist layer 18. That is, there have been problems associated with the prior art, including that anisotropic (directional) etching of a Cu wiring layer is impracticable.